1. Field of the Invention
The invention relates generally to data processing systems and, more particularly, to the storage and retrieval of information within a data processing system.
2. Description of the Related Art
The general purpose microprocessor has continued its phenomenal growth both in functionality and in popularity. However, many applications exist wherein the functionality and flexibility of the microprocessor instruction set can compromise the performance of the general purpose microprocessor. Consequently, a group of limited instruction set microprocessors, typically referred to as digital signal processors (DSP), has been developed. Digital signal processors have also seen a greatly expanded market as new applications have been identified and new architectures have been developed.
A typical data processing system 10 using a digital signal processor 11 for the actual processing of data is shown in FIG. 1. The digital signal processor 11 receives input signals, processes these signals, and transmits the processed signals as output signals. Coupled to the digital signal processor 11 is an X memory array 12 and a Y memory array 14. The X memory array 12, and the Y memory array 14, can include a memory unit 25 and can include one or more peripheral units 22. The memory unit 25 can be a conventional memory unit, while the peripheral unit 22 can be a conventional memory unit or can have a different functionality. Typically, the memory unit 25 includes a read-only-memory (ROM) portion 252 and a random-access-memory (RAM) portion 254. The ROM memory portion 252 can be used to store signal groups that will not be subject to change, while the RAM memory portion 254 is used to store data signal groups that have been or can be processed. By way of specific example, the input signals to the digital signal processor 11 can be encoded communication signals. The communication signals can be decoded by the digital signal processor 11, the X or Y memory unit storing intermediate and final results until transmission of the decoded signals. As will be clear to those acquainted with the processing of communication signals, the encoding and decoding of signals in a communication system can be computation-intensive and can require a large amount of memory. Similarly, the processing of speech, whether as part of a communication system or for other purposes, is also computation-intensive. These applications are typical of the processing activity to which digital signal processors have been advantageously applied.
However, while the restricted instruction set has been one of the keys to the high computational performance of the digital signal processors, this restricted instruction set has resulted in some limitations. For example, some of the techniques that are particularly convenient for programmers in the operation of the general purpose microprocessor are not available in the digital signal processors. These techniques can be used to conserve memory use and/or can be used to accelerate computations. Some of the techniques that are typically not as efficient in a digital signal processor are bit-field operations, stacks, and indirect addressing.
With respect to indirect addressing specifically, this technique involves identifying a final address location by the contents of an intermediate address location, i.e., the intermediate location being directly addressed and the final address being indirectly accessed through the contents of the intermediate address location. A need has therefore been felt for apparatus and method having the feature that an operation equivalent to indirect addressing can be achieved in a digital signal processor environment. A need has also been felt for an additional feature in a digital signal processor environment that is the operational equivalent to indirect addressing would not require additional functionality in the digital signal processor itself. A need has further been felt for a technique in the digital signal processor environment having the feature that the indirect addressing is implemented without alteration of the digital signal processor itself. A need has been also been felt for a technique in the digital signal environment for providing for sequential addressing of memory locations that can operate independently of the operation of the digital signal processor.
The aforementioned and other features are accomplished, according to the present invention, by providing a random access peripheral unit having a ROM memory, a control unit, and dual-port RAM memory. The digital signal processor transmits an address signal group to the X (or Y) memory unit. The address signal group is entered into the control unit. The control unit applies a portion of the address signal group to the ROM memory. The address signal group accesses a location in the ROM memory. The accessed (indirect) address memory location stores an address signal group that can be used by the control unit to access a location in the RAM memory. In this manner, a location in the RAM memory can be accessed for reading or writing of information. In addition, locations in the RAM memory can be accessed directly by the digital signal processing unit. In a second embodiment of the present invention, the control unit includes a pointer register and associated registers that permit the accessing of a sequence of locations in the RAM memory. In either embodiment, a storage location in a memory unit can be accessed by an address that does not correspond to the physical address of the storage location. And in either embodiment, the contents of the dual-port RAM memory can be accessed either through the control unit or can be accessed directly by the processing unit.